The present invention relates to a semiconductor device having a multilayer wiring structure, and particularly to a semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and a process for fabricating the same.
In semiconductor devices having multilayer wiring structures, wiring formed from aluminum-based alloys has been widely used. In such multilayer wiring, in general, pad electrodes are formed on the wiring on the uppermost layer, and external terminals are electrically connected to the pad electrodes through bonding wires or the like.
Recently, to achieve high speed and high performance of semiconductor devices, there is a tendency to use wiring formed from an alloy comprising, as a main component, copper which has low resistance and high reliability, so as to decrease wiring delay (or wiring resistance) or to increase the permissible current density of wiring.
FIGS. 20A to 20L show the steps of fabricating a semiconductor device using copper for wiring.
Referring to FIG. 20A, first, a semiconductor element 6 such as an MOS transistor comprising an insulating layer 2 for isolating the element, a gate-insulating layer 3, gate electrodes 4 and an impurity-diffusion layer 5 is formed on a semiconductor substrate 1. Then, an underlying insulating film 51 is deposited over a whole surface of the semiconductor element 6 by the thermal chemical vapor deposition process (thermal-CVD) or the plasma chemical vapor deposition process (plasma CVD). The underlying insulating film 51 has a three-layer structure which comprises an insulating layer 51a composed of a silicon oxide layer or a silicon oxide layer containing impurities such as phosphorous (P) and boron (B), a silicon nitride layer 51b serving to stop etching in the course of forming a wiring groove, and an insulating layer 51c such as a silicon oxide layer for forming the wiring groove.
Next, as shown in FIG. 20B, a contact hole 52 and a first wiring groove 53 are formed at predetermined positions on the underlying insulating film 51 by photolithography and etching. In this stage, the silicon nitride layer 51b has a high etching selective ratio with respect to the silicon oxide layer 51c, and thus serves as the stopper layer in the step of forming the first wiring groove 53.
Next, as shown in FIG. 20C, a barrier metal layer 54a and a tungsten (W) layer 54b are deposited on the overall surface to fill the contact hole 52 and the first wiring groove 53. As the barrier metal layer 54a, for example, a laminated film of a titanium (Ti) layer with a thickness of 10 to 50 nm and a titanium nitride (TiN) layer with a thickness of 50 to 100 nm is used to achieve good ohmic contact with the impurity-diffusion region 5 of the semiconductor device 6.
Next, as shown in FIG. 20D, the tungsten layer 54b and the barrier metal layer 54a except for the contact hole 52 and the first wiring groove 53 are removed by chemical mechanical polishing (hereinafter referred to as CMP) using a hydrogen peroxide-based alumina abrasive so as to form a first buried metal wiring layer 54 which has a thickness of about 100 to about 300 nm.
Next, as shown in FIG. 20E, a first interlayer insulating film 55 having a three-layer structure consisting of an insulating layer 55a of a silicon oxide or the like, a silicon nitride layer 55b and an insulating layer 55c of a silicon oxide or the like is deposited on the surface of the first metal wiring layer 54 in the same manner as in FIG. 20B. Subsequently, a first via hole 56 and a second wiring groove 57 are formed at predetermined positions on the first interlayer insulating film 55 by photolithography and etching.
Next, as shown in FIG. 20F, an underlying layer 58a and copper layers 58b and 58c are deposited on the overall surface so as to fill the first via hole 56 and the second wiring groove 57. The underlying layer 58a serves to prevent the copper from diffusing into the ambient insulating layer of silicon oxide or the like. As the underlying layer 58a, generally, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a lamination (TaN/Ta) of tantalum and tantalum nitride layers, a titanium nitride layer (TiN), a lamination (TiN/Ti) of a titanium layer and a titanium nitride layer or the like is used.
Further, a copper seed layer 58b is deposited on the overall surface as an underlying layer for electrolytic plating, and then, a copper plating layer 58c is deposited on the overall surface by the electrolytic plating process using a plating solution containing, for example, copper sulfate as a main component.
Next, as shown in FIG. 20G, the copper layers 58c and 58b and the underlying layer 58a except for the first via hole 56 and the second wiring groove 57 are removed by CMP to form a second buried metal wiring layer 58. The thickness of the second metal wiring layer 58 is, for example, about 300 to about 500 nm.
Next, as shown in FIG. 20H, a second interlayer insulating film having a four-layer structure consisting of a silicon nitride layer 59a for preventing copper from diffusing, an insulating layer 59b of silicon oxide or the like, a silicon nitride layer 59c and an insulating layer 59d of silicon oxide or the like is formed on the surface of the second metal wiring layer 58. Subsequently, a second via hole 60 and a third wiring groove 61 are formed at predetermined positions on the second interlayer insulating film 59 by photolithography and etching.
Similarly, an underlying layer 62a and copper layers 62b and 62c are deposited on the overall surface so as to fill the second via hole 60 and the third wiring groove 61, and then, the copper layers 62c and 62b and the underlying layer 62a except for the second via hole 60 and the third wiring groove 61 are removed by CMP to form a third buried metal wiring layer 62.
Next, as shown in FIG. 20I, a third interlayer insulating film 63 having a four-layer structure consisting of a silicon nitride layer 63a, an insulating layer 63b of silicon oxide or the like, a silicon nitride layer 63c and an insulating layer 63d of silicon oxide or the like is deposited on the surface of the third metal wiring layer 62 in the same manner as in FIG. 20H. Subsequently, a third via hole 64 and a fourth wiring groove 65 are formed at predetermined positions on the third interlayer insulating film 63 by photolithography and etching. Then, an underlying layer 66a and copper layers 66b and 66c are deposited on the overall surface so as to fill the above hole and groove. Then, unnecessary portions of the copper layers 66c and 66b and the underlying layer 66a are removed by CMP so as to form a fourth buried metal wiring layer 66.
In this connection, the fourth and the fifth metal wiring layers are used as long-distance wiring and a power source line, and therefore have higher thickness as compared with the underlying first to third metal wiring layers.
Next, as shown in FIG. 20J, a forth interlayer insulating film 67 having a four-layer structure consisting of a silicon nitride layer 67a, an insulating layer 67b of silicon oxide or the like, a silicon nitride layer 67c and an insulating layer 67d of silicon oxide or the like is deposited on the forth metal wiring layer 66 in the same manner as in FIG. 20I. Subsequently, a forth via hole 68 and a fifth wiring groove 69 are formed at predetermined positions on the forth interlayer insulating film 67, and then, an underlying layer 70a and copper layers 70b and 70c are deposited on the overall surface to fill the above hole and the above groove. Then, unnecessary portions of the copper layers 70c and 70b and the underlying layer 70a are removed by CMP to form a fifth buried metal wiring layer 70.
Usually, a pad electrode 71 for use in connecting an external terminal is concurrently formed on the uppermost layer. Metal wiring with a thickness of at least 1.0 μm is usually used for the pad electrode, taking into account a wire bonding step.
Next, as shown in FIG. 20K, a dense silicon nitride layer 72a as a copper diffusion-preventive layer is deposited on the fifth metal wiring layer 70, and then, a protective insulating layer 72b such as a silicon nitride layer, silicon oxide layer, or their laminated film is deposited with a thickness of about 1.0 μm.
Subsequently, if necessary, a buffer coating layer 73 of polyimide or the like may be formed with a thickness of about 5 to about 10 μm as a second protective insulating layer on the above protective insulating layer, and an opening 74 is formed at a predetermined position on the pad electrode 71.
Next, the reverse side of the chip divided from the semiconductor substrate 1 is bonded to a lead frame or a mount substrate with a resin or solder (not shown). Then, as shown in FIG. 20L, a wire 75 of gold or copper is bonded to an exposed portion of the copper wiring layer in the opening 74 of the pad electrode by means of ultrasonic waves, thermo compression bonding or the like, so that an intermetallic compound layer or an inter diffusion layer 76 is formed on the contact interface between the pad electrode 71 and the bonding wire 75.
Finally, a whole of the surface of the chip is sealed with a mold resin 77 to complete the semiconductor device shown in FIG. 19.
However, the conventional semiconductor device with the above structure has a problem in that, as shown in FIG. 21A, the pad electrode 71 is formed from copper which is easily oxidized. Therefore, an oxidized layer 78 with a thickness of about 5 to about 10 nm, which is relatively thick, is formed soon on the surface 74 of the pad electrode 71 as shown in the enlarged view of FIG. 21B.
In case where wire bonding is carried out as shown in FIG. 22A, the oxidized layer 78 can not be sufficiently destructed by means of ultrasonic waves or thermo compression bonding, because the oxidized layer 78 of copper is thickly formed on the surface of the pad electrode 71. Accordingly, it is impossible to uniformly form the intermetallic compound layer 76 on the interface between the bonding wire 75 and the pad electrode 71 as shown in the enlarged view of FIG. 22B, and thus, it is hard for their contact portion to have sufficient bonding strength. This is a serious problem for a highly integrated semiconductor device because it is inevitable to reduce the size of pad electrodes and the diameter of wire more and more in association with a tendency of high degree of integration in semiconductor devices.
On the other hand, where a pad electrode is formed from aluminum which forms a relatively thin oxidized layer on the surface, a decrease in bonding strength due to the formation of the oxidized layer arises a problem in association with the tendency of high degree of integration in semiconductor devices and smaller sizes of pad electrodes.
To overcome this problem, Japanese Kokai Patent Publication No. 5-82581/1993 discloses an aluminum pad electrode covered with a gold layer which is hardly oxidized, so as to protect the surface of the pad electrode from oxidization. However, in spite of such a structure, the bonding strength is still insufficient in the pad electrode of this highly integrated semiconductor device, resulting in poor reliability of the semiconductor device.
The present inventors have intensively researched this problem, and found that an oxidation seed enters the interface between the metal layer coating the surface of the pad electrode and the insulating layer coating the periphery of the metal layer, that an oxidized layer forms particularly around the periphery of the surface of the pad electrode, and that such an oxidized layer would give adverse influence on the pad surface if the area of the pad is small, thereby degrading the bonding strength.
That is, an object of the present invention is to provide a semiconductor device in which the surfaces of the pad electrodes can be protected from oxidation despite its highly integrated structure and in which the connecting strength to external terminals is improved.